module wdt_fpga(clk,rst,key1,led,clkwdt);
  input clk,rst,key1;
  output reg led;              //狗叫则灯亮
  output reg clkwdt;
 
  reg bark;
  reg [16:0]cnt; 
  reg [24:0]counter;                    
  wire flag;                    //喂狗标志位

  parameter cnt_full = 5000;
  
  always @(posedge clk or negedge rst) begin        //分频器(周期0.002秒)
	 if(~rst) begin
		 clkwdt  <= 0;			
		 counter <= 0;
	 end
	  
	 else if(counter == 11999) begin                   
		 counter <= 0;
		 clkwdt <= ~clkwdt;
	 end 
	 
	 else begin
		 counter <= counter + 1;
	 end
  end
  
  assign flag = ~key1;
  
  always @(*) begin
	 if(bark)
		led = 0;
	 else
		led = 1;
  end
  
  
  always @(posedge clkwdt or negedge rst) begin
	 if(~rst) begin
      cnt <= 0;
      bark <= 0;
	
    end
	 
	 else if(flag) begin
		cnt <= 0;
		bark <= 0;
	 end
	 
	 else if(cnt == cnt_full) begin
		cnt <= 0;
		bark <= 1;
	 end
		
    else begin
		cnt <= cnt + 1;
		bark <= bark;
	 end
	 
	 
	end                      // always end 
 
endmodule
  
   
    
    